1. Field of the Invention
The present invention relates to electronic device packaging. More specifically, it relates to improvements in TAB packaging for semiconductor chip devices and has particular utility with those devices having high numbers of output lines.
2. Description of the Prior Art
Conventional TAB packaging is well known in the art. Typically, a polymer film having a length dimension much greater than its width for eventual storage on a reel-like device is provided with evenly spaced apertures. Using conventional techniques, conductive lines are supplied around each aperture with their ends cantilevered into the aperture. These ends are subsequently attached as appropriate to a semiconductor device, one per aperture, as for example shown in U.S. Pat. No. 3,887,783 to Comette, FIG. 1. A similar structure is shown in Japanese patent abstract 125637.
TAB packages generally enable packaging of chips with a high number of I/O connections and can be easily automated for mass handling. However, such a package has higher inductance in connecting leads than corresponding prior art connection technologies such as used with pin grid array packaging.
IBM Technical Disclosure Bulletin, Vol. 28, No. 7, December, 1985, page 2827, relates to low inductance decoupling capacitor connection and discloses placing a capacitor on a module at each corner of the chip.
U.S. Pat. No. 4,577,214 to Schaper discloses a semiconductor package with low inductance power/ground leads in the package and uses a capacitor. Similarly, U.S. Pat. No. 4,598,307 recognizes the need for mounting a bypass capacitor as close as possible to an integrated circuit chip and uses specific unused real estate area of a dual in-line package for mounting a capacitor.
U.S. Pat. No. 4,539,472 discloses interconnecting a plurality of TAB devices as opposed to the conventional technique of having one logic chip within a frame of the tape. Additionally, means are disclosed for connecting apparently from the underside of the active integrated circuit chip device to a lead pattern formed on a substantially rigid substrate.